In advanced technology nodes of integrated circuit industry, the critical dimensions of semiconductor devices become smaller and smaller. Various new compositions and structures are adopted. For examples, a high k dielectric material and metal are used to form a gate stack of a field-effect transistor (FET) such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Three dimensional (3D) fin field effect transistors (FINFETs) are also used. Contact resistance plays a key factor to boost Ion/Ioff performance on FinFET devices, especially below N10 generation. Even though silicide is formed on the source and drain to reduce the contact resistance. However, the existing method cannot effectively reduce the contact resistance while maintaining other parameters of the devices and the overall of the device performance. Especially, the contact area is constrained due to the device scaling. Higher implantation for dopant boosting may improve the contact resistance but the high concentration dopant may diffuse to the channel and shift threshold voltage.
What is needed is a semiconductor structure with reduced contact resistance and the method making the same to address the above issues